Vertical junction field effect transistor with mesa termination and method of making the same

ABSTRACT

A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

This application is a continuation-in-part of U.S. patent applicationSer. No. 11/415,279, filed on May 2, 2006, now allowed, which isincorporated by reference herein in its entirety.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

This invention was made with U.S. Government support under Air ForceResearch Laboratory Agreement No. F33615-02-D-2103. The U.S. Governmentmay have certain rights in this invention.

BACKGROUND

1. Technical Field

The application relates generally to semiconductor devices and methodsof making the same, in particular, to vertical junction field effecttransistors (JFETs) having a mesa edge termination.

2. Background of the Technology

Monolithic devices comprising Schottky and PiN diodes are known (See,for example, U.S. Pat. No. 6,861,723 and [1]). U.S. Pat. No. 6,573,128discloses a SiC Junction Barrier Schottky (JBS)/Merged P-I-N Schottky(MPS) grid that is formed of Schottky metal deposited on p-type islandsdefined by plasma etching through an epitaxially grown layer. However,this structure is unable to effectively protect itself from a surgecurrent because of the absence of p-type ohmic contacts on the p-typeregions and insufficient conductivity modulation caused by low doping ofp-type regions.

U.S. Pat. Nos. 6,104,043 and 6,524,900 disclose JBS/MPS diodes havingheavily doped p-type regions formed by ion implantation. If ohmiccontacts to heavily doped implanted p-type regions are formed asdisclosed in U.S. Pat. No. 6,104,043, however, the conductivitymodulation in the drift region of such a structure suffers from lowminority carrier lifetime caused by residual implantation damage evenafter thermal anneal at high temperature.

U.S. Pat. No. 4,982,260 describes the definition of p-type emitterregions by etching through the heavily doped p-type well created bydiffusion. However, since diffusion of dopants into SiC occurs veryslowly at even extremely high temperatures, as a practical matter, ap-type well can only be formed in n-type SiC by ion implantation, whichhas the disadvantage described above.

U.S. Pat. No. 6,897,133 describes forming p-type emitter regions byetching trenches in n-type material and filling them with p-typeepitaxially grown material followed by chemical-mechanical polishing oranother planarization step. This device, however, has JFET regions thatmay significantly limit current conduction under normal operatingconditions.

SiC devices that employ mesa edge termination are also known [2]. Mesaedge termination technology for Si, however, is generally inapplicableto SiC device technology due to difficulties related to etching of SiCand removing the damage caused by the etching process (See, for example,U.S. Pat. No. 5,449,925 and [3]). The use of mesa termination in 4H—SiCdiodes has also been disclosed (U.S. Pat. No. 6,897,133, [4], and [5]).

There still exists a need for semiconductor devices having improvedproperties.

SUMMARY

A semiconductor device is provided which comprises:

an n-type substrate;

a first layer of n-type semiconductor material on the n-type substrate,wherein the first layer of n-type semiconductor material isnon-coextensive with the underlying n-type substrate thereby forming amesa having an upper surface and sidewalls;

a plurality of raised n-type regions on the upper surface of the mesa,the raised n-type regions comprising an upper layer of n-typesemiconductor material on a lower layer of n-type semiconductor materialwhich is on the upper surface of the mesa, the raised n-type regionshave an upper surface comprising the upper layer of n-type semiconductormaterial and sidewalls comprising an upper sidewall portion comprisingthe upper layer of n-type semiconductor material and a lower sidewallportion comprising the lower layer of n-type semiconductor material;

p-type regions between and adjacent the raised n-type regions and alongthe lower sidewall portion of the raised regions;

a first dielectric layer on the sidewalls of the raised regions, on thep-type layer between and adjacent the raised regions and on thesidewalls of the mesa;

one or more additional layers of dielectric material on the firstdielectric layer on the sidewalls of the mesa and between and adjacentthe raised regions on the upper surface of the mesa;

source ohmic contacts on the upper surfaces of the raised regions;

a gate ohmic contact on the implanted p-type layer;

a drain ohmic contact on the substrate layer opposite the first layer ofsemiconductor material;

one or more layers of metal on the source ohmic contacts;

one or more layers of metal on the gate ohmic contact; and

one or more layers of metal on the drain ohmic contact.

A method of making a semiconductor device is provided which comprises:

selectively etching through a first layer of n-type semiconductormaterial through openings in a mask to form raised regions and to exposean underlying second layer of n-type semiconductor material, wherein thesecond layer of n-type semiconductor material is on a third layer ofn-type semiconductor material which is on an n-type substrate;

implanting p-type dopants into exposed surfaces of the second layer ofn-type semiconductor material through openings in the mask to formimplanted p-type regions;

removing the mask;

selectively etching through the third layer of n-type semiconductormaterial in a peripheral region of the device to expose underlyingn-type substrate and to form a mesa having sidewalls and an uppersurface, wherein the raised regions and the implanted p-type regions areon the upper surface of the mesa;

forming a first dielectric layer on the sidewalls of the mesa, onexposed surfaces of the substrate adjacent the mesa sidewalls, on theimplanted p-type regions on the upper surface of the mesa and on thesidewalls and upper surfaces of the raised regions;

selectively etching the dielectric layer to expose the upper surfaces ofthe raised regions and at least a portion of the implanted p-type regionon the upper surface of the mesa adjacent the raised regions;

forming source ohmic contacts on the exposed upper surfaces of theraised regions;

forming a gate ohmic contact on the exposed implanted p-type region onthe upper surface of the mesa;

forming a drain ohmic contact on the n-type substrate opposite the thirdlayer of n-type semiconductor material;

forming one or more additional dielectric layers between and adjacentthe raised regions on the upper surface of the mesa, on the mesasidewalls and on the substrate adjacent the mesa;

selectively etching through the one or more additional dielectric layersto expose the source ohmic contacts and the gate ohmic contact;

forming one or more metal layers on the source ohmic contacts;

forming one or more metal layers on the gate ohmic contact; and

forming one or more metal layers on the drain ohmic contact.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-section of a device according to oneembodiment.

FIG. 2 is a schematic process flow for the fabrication of the device ofFIG. 1.

FIG. 3 shows an exemplary layout of p-type regions on the device mesa.

FIG. 4A is a schematic cross-section of a mesa-terminated 4H—SiC PiNdiode.

FIG. 4B is a graph showing electric field distribution along the mesasidewall for different interface charge densities at a reverse bias of600 V.

FIG. 5 is a graph showing the dynamics of electric field distributionalong the mesa sidewall in 4H—SiC PiN diode assuming zero interfacecharge density.

FIG. 6 illustrates non-destructive avalanche breakdown measured on amesa-terminated diode with 5.7 μm, 1.25×10¹⁶ cm⁻³ base layer.

FIGS. 7A and 7B are wafer maps showing measured breakdown voltages (A)and extracted E_(IDMAX) (B) on the same substrate. Reverse biasmeasurements were done with 25 V step. Devices with V_(B)<850 V areexcluded from the maps.

FIG. 8 is a graph showing a comparison of yield distribution between4H—SiC PiN diodes with different edge termination techniques.

FIG. 9 is a schematic illustrating a vertical junction field effecttransistor (VJFET) with a mesa termination

FIGS. 10A-10I are schematics illustrating a method of making a verticaljunction field effect transistor (VJFET) with a mesa termination asshown in FIG. 9.

FIG. 11A is a schematic cross-section of the mesa termination region ofa VJFET showing the interface charge region.

FIG. 11B is a graph showing the electric field distribution along themesa sidewall for the VJFET shown in FIG. 11A.

REFERENCE NUMERALS

-   -   1 N-type SiC substrate (e.g., doping concentration of >1×10¹⁸        cm⁻³)    -   2 Epitaxially grown SiC layer (n-type). Representative        thicknesses of this layer can be 0.75 μm-100 μm and        representative doping concentrations can be 5×10¹⁴-1×10¹⁷ cm⁻³.    -   3 Epitaxially grown SiC layer (p-type). Representative        thicknesses of this layer can be 0.2-5 μm and representative        doping concentrations can be >5×10¹⁸ cm⁻³.    -   4 Single or multilayer dielectric stack    -   5 Ohmic contact to n-type SiC material    -   6 Ohmic contact to p-type SiC material    -   7 Schottky contact    -   8 Front-side final metallization    -   9 Backside final metallization

The reference numerals used in FIGS. 9 and 10A-10I are defined in thefollowing table. Also provided are exemplary and non-limiting layerthicknesses and doping concentrations for some of the layers or featuresof the device depicted in these Figures.

11 N-type substrate (e.g., doping level > 1 × 10¹⁸ cm⁻³) 12 Epitaxiallygrown layer (n-type) (e.g., 1-350 μm thickness, 2 × 10¹⁴-1 × 10¹⁷ cm⁻³doping conc.) 13 Epitaxially grown layer (n-type) (e.g., 0.5-5 μmthickness, 5 × 10¹⁵-5 × 10¹⁷ cm⁻³ doping conc.) 14 Epitaxially grown orimplanted layer (n-type) (e.g., >0.1 μm thickness, >1 × 10¹⁸ cm⁻³ dopingconc.) 15 Implantation mask layer (e.g., PECVD oxide > 1.5 μm) 16Selectively formed etch mask (e.g., Ni > 500 Å) 17 Implanted regions(p-type) (e.g., >0.1 μm thickness, >1 × 10¹⁸ cm⁻³ doping conc.) 18 Firstdielectric layer (e.g., thermally-grown SiO₂, >500 Å thickness onvertical surfaces) 18a Additional dielectric layer or layers (e.g.,single-layer or multi-layer) 19a Source ohmic contact 19b Gate ohmiccontact 19c Drain ohmic contact 20a Source final metallization (e.g.,single or multi-layer) 20b Gate final metallization (e.g., single ormulti-layer) 20c Drain final metallization (e.g., single or multi-layer)

DETAILED DESCRIPTION

According to one embodiment, the device comprises monolithicallyintegrated Schottky barrier diodes and p-type/intrinsic/n-type (PiN)junction diodes connected in parallel fashion. An exemplary device isshown in FIG. 1. At normal operating conditions, the device acts as aSchottky barrier diode wherein the majority of the current flow occursthrough the Schottky contacts. At surge current conditions, however, thecurrent flows mainly through the p-n junctions because of significantreduction of drift resistance due to conductivity modulation at highcurrent densities. This phenomenon can be illustrated by the followingmathematical expression that computes the specific resistance of thebase region of a PiN diode with forward current density J_(F) [6]:

$\begin{matrix}{{R\left( J_{F} \right)} = \frac{t}{{q \cdot \mu_{n} \cdot N} + \frac{\left( {\mu_{n} + \mu_{p}} \right) \cdot J_{F} \cdot \tau_{a}}{t}}} & (1)\end{matrix}$In this formula, μ_(n) and μ_(p) are electron and hole mobilitiesrespectively, τ_(α) is ambipolar lifetime, and t and N represent thethickness and the doping concentration respectively of the drift (base)region. The optimal values of t and N can be chosen for the normaloperation conditions (i.e., no conductivity modulation) as a function oftargeted blocking voltage V_(B) and maximum plane-junction electricfield E_(IDMAX) using the following formulas [7]:

$\begin{matrix}{{{t_{opt}\left( {V_{b},E_{1\;{DMAX}}} \right)} = {\frac{3}{2} \cdot \frac{V_{b}}{E_{1\;{DMAX}}}}}{{N_{opt}\left( {V_{b},E_{1{DMAX}}} \right)} = {\frac{4}{9} \cdot \frac{ɛ_{0} \cdot ɛ_{r}}{q} \cdot \frac{E_{1{DMAX}}^{2}}{V_{b}}}}} & (2)\end{matrix}$

An exemplary fabrication process of the described device may consist ofthe following macro-steps as shown in FIG. 2:

-   -   1. Growth of epitaxial stack    -   2. Selective plasma etches through p-type layer (3) down to        n-type layer (2) to form p-type islands, and through p-type        layer (3) and n-type layer (2) down to n-type substrate (1)        layer to form device mesa, followed by thermal oxidation and        optional deposition of additional dielectric layers to form        dielectric stack (4). Thermal oxidation step consumes surface        damage caused by plasma etch of SiC.    -   3. Formation of ohmic contact (5) on backside of n-type        substrate (1) resulting in ohmic contact to n-type material        followed by selective formation of ohmic contacts (6) on p-type        islands resulting in ohmic contacts to p-type material.    -   4. Deposition of Schottky contact (7) and front-side final metal        (8) resulting in metal stack (7-8) followed by deposition of        backside final metal (9) resulting in backside metallization.        Metallization steps 3 and 4 include selective etching (e.g., wet        etching) through the dielectric stack (4) in order to expose SiC        surface prior to metal deposition and remove surface damage        caused by plasma etching of SiC.

FIG. 3 shows an exemplary layout of a heavily doped p-type region (30)in a device according to one embodiment. Although a single square shapedregion is shown in FIG. 3, the shape, number, and area of the p-typeregions may vary. An outer p-type ring 32 is also shown as is the devicemesa edge 34. The outer p-type ring 32 protects metal-semiconductorjunctions from the highest electric field that occurs at the edge of thedevice. A metal-semiconductor junction exhibits significantly higherleakage current than that of a p-n junction for the same appliedelectric field due to thermionic field emission through the Schottkybarrier [8].

As shown in FIG. 1, the described device employs mesa edge terminationfor protection from high electric field. Mesa etching through the mainjunction and voltage blocking layer is theoretically the most efficientmethod to eliminate electric field enhancement caused by two-dimensionaleffects. Assuming that there is no interface charge on the mesasidewalls, the electric field distribution in the device can becalculated using the one-dimensional Poisson equation.

The method described above is relatively simple from the fabricationpoint of view because it does not need difficult-to-control andexpensive fabrication steps such as high-temperature ion implantationand post-implant annealing required, for example, to form analuminum-implanted junction termination extension (JTE) edgetermination. Because the depletion region in mesa-terminated devicesdoes not spread laterally under reverse bias, this method also allowsfor more efficient use of area than with other edge terminationtechniques, resulting in lower cost and higher yield.

Despite the numerous advantages, mesa edge termination requires carefulsidewall passivation in order to minimize the interface trap density andthe amount of fixed charge stored at or near the mesa sidewalls. FIGS.4A and 4B illustrate the influence of the interface charge on the fielddistribution along the sidewall of a mesa-terminated 4H—SiC PiN diodereverse biased to 600 V. In particular, FIG. 4A is a schematiccross-section of a mesa-terminated 4H—SiC PiN diode. FIG. 4B is a graphshowing electric field distribution along the mesa sidewall fordifferent interface charge densities at a reverse bias of 600 V. Asshown in FIG. 4B, a certain amount of negative charge in the passivationlayer can be beneficial, since it further reduces the maximum electricfield along the mesa sidewalls. In practice, however, the fixed chargein the silicon dioxide used for passivation in SiC devices is usuallypositive and a negative charge introduced by interface traps andelectrons injected into the passivation layer may cause memory effectsand compromise high-temperature performance of the device.

To illustrate the almost one-dimensional nature of the fielddistribution along the mesa sidewalls, the surface electric field hasbeen investigated as a function of applied reverse bias.

FIG. 5 shows the family of mesa surface field distributions at reversevoltages from 100 V to 900 V when no surface charge is present. As shownin FIG. 5, the surface field experiences a linear increase with appliedreverse bias, and the field distribution maintains adequate linearityalong the mesa sidewall regardless of the applied bias.

EXPERIMENTAL

4H—SiC PiN diodes were fabricated with a voltage blocking layer designedfor the maximum plane-junction electric field E_(IDMAX)=1.8 Mv/cm atV_(B)=600 V and employing mesa etching for edge termination. Aftercompleting the fabrication, on-wafer I-V measurements were done inFluorinert™ using Keithley 237 SMU and a Tektronix 576 curve tracer. Thedevices with both types of edge termination demonstrated a reversibleavalanche breakdown. FIG. 6 shows a non-destructive avalanche breakdownmeasured on a mesa-terminated diode using a Tektronix 576 curve tracer.Wafer-scale measurements of the breakdown voltage were done with a 25 Vstep increment of reverse bias. A typical V_(B) map is shown in FIG. 7A.The maximum 1-D electric field E_(IDMAX) was then extracted from themeasured epi parameters and breakdown voltage using expression

$\begin{matrix}{E_{1{DMAX}} = {\frac{V_{B}}{t} + \frac{q \cdot t \cdot N}{2 \cdot ɛ_{0} \cdot ɛ_{r}}}} & (3)\end{matrix}$On mesa-terminated diodes, the mean value of this field was found to beof 2.4 MV/cm with a standard deviation σ=35 kV/cm. Such small standarddeviation from the mean value corresponded to E_(IDMAX) uniformity of1.45%. A map of E_(IDMAX) is shown in FIG. 7B. The experimentallyachieved E_(IDMAX) of 2.4 MV/cm corresponds to 93% of the “theoreticalvalue” of critical electric field in 4H—SiC given by Reference [9]:

$\begin{matrix}{E_{c} = {\frac{2.49 \times 10^{6}}{1 - {\frac{1}{4}{\log_{10}\left( \frac{N_{D}}{10^{16}{cm}^{- 3}} \right)}}}{V/{{cm}.}}}} & (4)\end{matrix}$

Although the charge conditions on the mesa sidewalls are unknown, thesimulation results suggest that the electric field may experience acertain non-linear increase as shown in FIGS. 4 and 5. In this case, theelectric field reaches its true critical value at the anode junctionthat triggers an avalanche breakdown. The majority of themesa-terminated devices measured on all 3 substrates (5584 of 8222tested, or 67.9%) demonstrated an average breakdown voltage ranging from925 V to 975 V. FIG. 8 shows a comparison between yield distributions ofthe diodes fabricated using mesa edge termination and a different edgetermination technique.

Although devices having a single layer of n-type SiC semiconductormaterial are described above, the device may comprise multiple layer ofn-type SiC semiconductor material. For example, the device may comprisea first layer of n-type SiC semiconductor material in contact with theSiC substrate layer and a second layer of n-type SiC semiconductormaterial on the first layer of n-type SiC semiconductor material. Thesecond layer of n-type SiC semiconductor material may have a lowerdoping concentration than the first layer of n-type SiC semiconductormaterial.

A vertical junction field effect transistor (VJFET) having a mesatermination is also provided. A device of this type is depicted in FIG.9. As shown in FIG. 9, this device comprises an n-type substrate (11)and a first layer of n-type semiconductor material (12) on thesubstrate. The first layer of n-type semiconductor material isnon-coextensive with the underlying n-type substrate (11) therebyforming a mesa having an upper surface and sidewalls. As shown in FIG.9, the device also comprises a plurality of raised n-type regions on theupper surface of the mesa. Each of the raised n-type regions comprisesan upper layer of n-type semiconductor material (14) on a lower layer ofn-type semiconductor material (13) which is on the upper surface of themesa. Each of the raised n-type regions also comprises an upper surfaceand upper sidewall portions comprising the upper layer of n-typesemiconductor material (14) and lower sidewall portions comprising thelower layer of n-type semiconductor material (13). The device alsocomprises p-type regions (17) between and adjacent the raised n-typeregions and along the lower sidewall portions of the raised regions. Asdepicted in FIG. 9, the device also comprises a first dielectric (e.g.,SiO₂) layer (18) on the sidewalls of the raised regions, on the p-typelayer between and adjacent the raised regions and on the sidewalls ofthe mesa. As also depicted in FIG. 9, the device comprises one or moreadditional layers of dielectric material (18 a) on the first dielectriclayer (18) on the sidewalls of the mesa and between and adjacent theraised regions on the upper surface of the mesa. Source ohmic contacts(19 a) are formed on the upper surfaces of the raised regions, a gateohmic contact (19 b) is formed on the implanted p-type regions (17) anda drain ohmic contact (19 c) is formed on the substrate layer (11)opposite the first layer of semiconductor material (12). Source metallayer (20 a) is formed on the source ohmic contacts, gate metal layer(20 b) is formed on the gate ohmic contact (19 b) and drain metal layer(20 c) is formed on the drain ohmic contact (19 c).

The device of FIG. 9 can be made by a method as set forth in FIGS.10A-10I. As shown in FIG. 10A, a first layer of n-type semiconductormaterial (14) is on a second layer of n-type semiconductor material (13)which is on a third layer of n-type semiconductor material (12) which ison an n-type substrate (11). The second and third layers of n-typesemiconductor material can be formed by epitaxial growth. The firstlayer can be formed by epitaxial growth on the second layer or byimplanting n-type dopants in the second layer. The first layer of n-typesemiconductor material can have a thickness of greater than 0.1 μmand/or a doping concentration of greater than 1×10¹⁸ cm³. The secondlayer of n-type semiconductor material can have a thickness of 0.5 to 5μm and/or a doping concentration of 5×10¹⁵ to 5×10¹⁷ cm⁻³. The thirdlayer of n-type semiconductor material can have a thickness of 1 to 350μm and/or a doping concentration of 2×10¹⁴ to 1×10¹⁷ cm⁻³.

As shown in FIG. 10B, an implantation mask layer (15) can be formed onthe upper surface of a first layer of n-type semiconductor material(14). The implantation mask layer (15) can be an SiO₂ layer formed by,for example, plasma enhanced chemical vapor deposition (PECVD). As alsoshown in FIG. 10B, an etch mask (16) can be selectively formed on theimplantation mask layer (15). Etch mask (16) can comprise nickel (Ni)and can have a thickness greater than 500 Angstroms.

As shown in FIG. 10C, the implantation mask layer (15) and the firstlayer of n-type semiconductor material (14) can be selectively etchedthrough openings in the etch mask (16) to form corresponding openings inthe underlying implantation mask layer (15) and to form the raisedregions thereby exposing the underlying second layer of n-typesemiconductor material. As also shown in FIG. 10C, the second layer ofn-type semiconductor material (13) can be partially etched into duringselective etching of the implantation mask layer (15) and the firstlayer of n-type semiconductor material (14).

As shown in FIG. 10D, p-type dopants can then be implanted into theexposed surfaces of the second layer of n-type semiconductor material(13) through openings in the implantation mask layer (15) to form p-typeregions (17). The p-type regions (17) can have a thickness of greaterthan 0.1 μm and/or a doping concentration of greater than 1×10¹⁸ cm⁻³.

As shown in FIG. 10E, etch mask (16) and implantation mask (15) can thenbe removed.

As shown in FIG. 10F, third layer of n-type semiconductor material (12)can then be selectively etched to expose underlying n-type substrate(11) in a peripheral region of the device to form the mesa. As alsoshown in FIG. 10F, a dielectric layer (18) can be formed on thesidewalls of the mesa, on exposed surfaces of the substrate, on theimplanted p-type regions on the upper surface of the mesa and on thesidewalls and upper surfaces of the raised regions. Dielectric layer(18) can be thermally grown SiO₂. Dielectric layer (18) can have athickness of greater than 500 Angstroms on the sidewalls of the mesa andon the sidewalls of the raised regions.

Dielectric layer (18) can then be selectively etched to expose the uppersurfaces of the raised regions and a portion of the implanted p-typeregion on the upper surface of the mesa adjacent the raised regions. Asshown in FIG. 10G, source ohmic contacts (19 a) can then be formed onthe exposed upper surfaces of the raised regions. As also shown in FIG.10G, a gate ohmic contact (19 b) can be formed on the exposed implantedp-type region on the upper surface of the mesa and a drain ohmic contact(19 c) can be formed on the n-type substrate opposite the third layer ofn-type semiconductor material.

As shown in FIG. 10H, a dielectric layer (18 a) can then be formedbetween and adjacent the raised regions on the upper surface of themesa, on the mesa sidewalls and on the substrate adjacent the mesa.Although a single additional dielectric layer (18 a) is depicted in FIG.10H, multiple additional dielectric layers can be used. As also shown inFIG. 10H, source metal layer (20 a), gate metal layer (20 b) and drainmetal layer (20 c) can then be formed on the source ohmic contacts (19a), gate ohmic contact (19 b) and drain ohmic contact (19 c),respectively, to form the device as shown in FIG. 10I. Although a singlemetal layer is depicted in FIG. 10H for the source gate and drain metal,multiple metal layers can also be used.

FIGS. 11A and 11B illustrate the electric field along the mesa sidewallof a VJFET device as set forth in FIG. 9. FIG. 11A shows a portion ofthe device near the mesa sidewall indicating the interface charge(Q_(int)). As shown, the dielectric material on the sidewall of the mesahas a dielectric constant (∈) of 3.9 which is representative of thedielectric constant for SiO₂. FIG. 11B is a graph of the electric field(MV/cm) along the mesa sidewall as a function of the distance from thetop edge of the mesa (in μm) for three different interface charge values(i.e., 2×10¹² cm⁻², 0 cm⁻² and −2×10¹² cm⁻²). As can be seen from FIG.10B, a negative charge in the passivation layer can reduce the maximumelectric field along the mesa sidewall.

An exemplary material for forming ohmic contacts is nickel. Other ohmiccontact materials for SiC, however, can also be used.

Suitable n-type dopants for SiC include nitrogen and phosphorous.Nitrogen is a preferred n-type dopant. Suitable p-type dopants forsilicon carbide include boron and aluminum. Aluminum is a preferredp-type dopant. The above materials are merely exemplary, however, andany n or p-type dopant for silicon carbide can be used.

Although specific doping levels and thicknesses of the various layers ofthe device are described above, the doping levels and thicknesses of thevarious layers can be varied to produce a device having desiredcharacteristics for a particular application.

Doping of the SiC layers can be performed in-situ during epitaxialgrowth of each of the layers on a SiC substrate. The SiC layers can beformed by any epitaxial growth method known in the art, including CVD,molecular beam and sublimation epitaxy. The doped SiC layers can beformed by doping in-situ during epitaxial growth wherein dopant atomsare incorporated into the silicon carbide during growth.

While the foregoing specification teaches the principles of the presentinvention, with examples provided for the purpose of illustration, itwill be appreciated by one skilled in the art from reading thisdisclosure that various changes in form and detail can be made withoutdeparting from the true scope of the invention.

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1. A semiconductor device comprising: an n-type substrate having a frontsurface and a back surface; a first layer of n-type semiconductormaterial on and in direct contact with the front surface of the n-typesubstrate, wherein the first layer of n-type semiconductor material isnon-coextensive with the underlying n-type substrate thereby forming amesa having an upper surface and sidewalls, wherein the upper surfaceand sidewalls of the mesa form an edge and wherein the front surface ofthe n-type substrate adjacent the edge is exposed; a plurality of raisedn-type regions on the upper surface of the mesa, the raised n-typeregions comprising an upper layer of n-type semiconductor material on alower layer of n-type semiconductor material which is on the uppersurface of the mesa, the raised n-type regions have an upper surfacecomprising the upper layer of n-type semiconductor material andsidewalls comprising an upper sidewall portion comprising the upperlayer of n-type semiconductor material and a lower sidewall portioncomprising the lower layer of n-type semiconductor material, wherein thelower layer of n-type semiconductor material has a different dopingconcentration than the first layer of n-type semiconductor material;p-type regions on the upper surface of the mesa between and adjacent theraised n-type regions and along the lower sidewall portion of the raisedregions, wherein the p-type regions are adjacent the edge of the mesa; afirst dielectric layer on the sidewalls of the raised regions, on thep-type layer between and adjacent the raised regions and on thesidewalls of the mesa; one or more additional layers of dielectricmaterial on the first dielectric layer on the sidewalls of the mesa andbetween and adjacent the raised regions on the upper surface of themesa; source ohmic contacts on the upper surfaces of the raised regions;a gate ohmic contact on the p-type regions; a drain ohmic contact on theback surface of the substrate layer opposite the first layer ofsemiconductor material; one or more layers of metal on the source ohmiccontacts; one or more layers of metal on the gate ohmic contact; and oneor more layers of metal on the drain ohmic contact.
 2. The semiconductordevice of claim 1, wherein the n-type substrate, the first layer ofn-type semiconductor material, the upper layer of n-type semiconductormaterial, the lower layer of n-type semiconductor material and thep-type regions each comprise a wide-bandgap semiconductor material. 3.The semiconductor device of claim 1, wherein the n-type substrate, thefirst layer of n-type semiconductor material, the upper layer of n-typesemiconductor material, the lower layer of n-type semiconductor materialand the p-type regions each comprise SiC.
 4. The semiconductor device ofclaim 1, wherein the n-type substrate has a doping concentration ofgreater than 1×10¹⁸ cm⁻³.
 5. The semiconductor device of claim 1,wherein the first layer of n-type semiconductor material has a dopingconcentration of 2×10¹⁴ to 1×10¹⁷ cm⁻³.
 6. The semiconductor device ofclaim 1, wherein the first layer of n-type semiconductor material has athickness of 1 to 350 μm.
 7. The semiconductor device of claim 1,wherein the lower layer of n-type semiconductor material has a dopingconcentration of 5×10¹⁵ to 5×10¹⁷ cm⁻³.
 8. The semiconductor device ofclaim 1, wherein the lower layer of n-type semiconductor material has athickness of 0.5 μm-5 μm.
 9. The semiconductor device of claim 1,wherein the upper layer of n-type semiconductor material has a dopingconcentration of greater than 1×10¹⁸ cm⁻³.
 10. The semiconductor deviceof claim 1, wherein the upper layer of n-type semiconductor material hasa thickness of greater than 0.1 μm.
 11. The semiconductor device ofclaim 1, wherein the p-type regions have a doping concentration ofgreater than 1×10¹⁸ cm⁻³.
 12. The semiconductor device of claim 1,wherein the p-type regions have a thickness of greater than 0.1 μm. 13.The semiconductor device of claim 1, wherein the first dielectric layeris an SiO₂ layer having a thickness of greater than 500 Angstroms on thesidewalls of the mesa and on the sidewalls of the raised regions. 14.The semiconductor device of claim 1, wherein the device comprises morethan one additional layer of dielectric material on the first dielectriclayer.
 15. The semiconductor device of claim 1, wherein the devicecomprises more than one layer of metal on each of the source, gate anddrain ohmic contacts.
 16. The semiconductor device of claim 1, whereinthe first layer consists of the n-type semiconductor material.
 17. Thesemiconductor device of claim 1, wherein the device comprises an n-typeconductive path between the source ohmic contact and the drain ohmiccontact when no voltage is applied to the gate.
 18. The semiconductordevice of claim 1, wherein the device is an n-channel vertical junctionfield effect transistor.
 19. The semiconductor device of claim 1,wherein the first dielectric layer is on the front surface of the n-typesubstrate adjacent the sidewalls of the mesa.
 20. The semiconductordevice of claim 1, wherein the interface between the n-type material onthe sidewalls of the mesa and the first dielectric layer on thesidewalls of the mesa has a charge density of 0 or a negative chargedensity.